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| General information | |
| Type | CPU / Microprocessor |
| Family | AMD Turion 64 X2 Mobile technology |
| Model number ? | TL-50 |
| CPU part number | TMDTL50HAX4CT |
| Box part number | TMDTL50CTWOF |
| Stepping codes | ADB5F CDB5F LDB5F LDB8F LDBDF |
| Frequency (MHz) ? | 1600 |
| Package | 638-pin lidless micro-PGA 1.38" x 1.38" (3.5 cm x 3.5 cm) |
| Socket | Socket S1 |
| Introduction date | May 17, 2006 |
| Price at introduction | $184 |
| Architecture / Microarchitecture | |
| Processor core | Taylor |
| Core stepping | F2 |
| Manufacturing process | 0.09 micron SOI |
| Data width | 64 bit |
| Number of cores | 2 |
| Floating Point Unit | Integrated |
| Level 1 cache size ? | 2 x 64 KB 2-way associative instruction cache 2 x 64 KB 2-way associative data cache |
| Level 2 cache size ? | 2 x 256 KB 16-way associative exclusive cache |
| Physical memory | 1 TB |
| Virtual memory (TB) | 256 |
| Features | |
| Low power features |
|
| On-chip peripherals |
|
| Electrical/Thermal parameters | |
| V core (V) ? | 1.075 / 1.1 |
| Maximum operating temperature (°C) ? | 95 |
| Thermal Design Power (W) ? | 31 |
| Condition | New |
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